1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device and a fabricating method of the same.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices are driven by optical anisotropy and polarization characteristics of a liquid crystal material. Liquid crystal molecules have a definite alignment as a result of their long, thin shapes and are arranged to have initial pretilt angles. The alignment direction can be controlled by applying an electric field. Specifically, variations in an applied electric field influence the alignment of the liquid crystal molecules. Due to optical anisotropy, the refraction of incident light depends on the alignment direction of the liquid crystal molecules. Thus, by properly controlling the applied electric field, an image that has a desired brightness can be produced.
In general, a liquid crystal display (LCD) device includes two substrates, which are spaced apart and face each other. A liquid crystal layer is interposed between the two substrates. Each of the substrates includes an electrode, and the electrodes of each substrate also face each other. Liquid crystal molecules of the liquid crystal layer are driven by an electric field, which is induced between the electrodes and is perpendicular to the substrates. The LCD device has a high transmittance and a large aperture ratio.
Of the different types of known liquid crystal displays (LCDs), active matrix LCDs (AM-LCDs), which have thin film transistors (TFTs) and pixel electrodes arranged in a matrix form, are the subject of significant research and development because of their high resolution and superior ability in displaying moving images.
FIG. 1 is an expanded perspective view schematically illustrating a related art LCD device. As shown in FIG. 1, the LCD device 51 includes a first substrate 5 and a second substrate 10, which are spaced apart from each other, and a liquid crystal layer (not shown) interposed therebetween. A black matrix 6, red, green and blue color filters 7a, 7b and 7c, and a common electrode 9 are formed on a surface of the first substrate 5 facing the second substrate 10. The common electrode 9 is transparent and covers the black matrix 6 and the color filters 7a, 7b and 7c. 
A plurality of pixel regions P is defined on a surface of the second substrate 10 facing the first substrate 5. A plurality of gate lines 14 and a plurality of data lines 26 cross each other to define the plurality of pixel regions P. A thin film transistor T is formed at each crossing point of the gate and data lines 14 and 26. A pixel electrode 32 is formed in each pixel region P and is connected to the thin film transistor T. The pixel electrode 32 includes a transparent conductive material having a high transmittance, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).
The first substrate 5 including the black matrix 6, the color filters 7a, 7b and 7c and the common electrode 9 may be referred to as a color filter substrate. The second substrate 10 including the gate lines 14, the data lines 26, the thin film transistors T and the pixel electrodes 32 may be referred to as an array substrate.
The array substrate is manufactured by a photolithographic process using a mask. The photolithographic process may be referred to as a mask process. The array substrate may be commonly manufactured by five or six mask processes.
The array substrate may be manufactured through the following five mask processes: a first mask process forming a gate electrode, a gate line and a gate pad; a second mask process forming an active layer and an ohmic contact layer on a gate insulating layer that covers the gate electrode, the gate line and the gate pad; a third mask process forming a data line, a data pad, and source and drain electrodes on the ohmic contact layer; a fourth mask process forming a passivation layer having a contact hole that exposes the drain electrode; and a fifth mask process forming a pixel electrode contacting the drain electrode through the contact hole.
However, because each of the mask processes includes several steps of cleaning, coating a photoresist layer, exposing through a mask, developing the photoresist layer, and etching, all the mask processes are very complicated and expensive. Therefore, reducing fabricating time and costs by simplifying the processes is an important issue to be resolved.
Accordingly, reducing the number of mask processes has been researched.
FIG. 2 is a plan view of an array substrate fabricated through four-mask processes according to the related art. For convenience of explanation, one pixel region is shown.
As shown in FIG. 2, gate lines 62 are formed along a first direction on a substrate 60, and data lines 82 are formed along a second direction on the substrate 60. The data lines 82 cross the gate lines 62 to thereby define pixel regions P. A gate pad 64 is formed at one end of each gate line 62, and a transparent gate pad terminal 112 contacts and covers the gate pad 64. A data pad 84 is formed at one end of each data line 82, and a transparent data pad terminal 114 contacts and covers the data pad 84.
A thin film transistor T is formed at each crossing point of the gate and data lines 62 and 82. The thin film transistor T includes a gate electrode 64, a first semiconductor layer 90a, a source electrode 94 and a drain electrode 96. The gate electrode 64 is connected to the gate line 62, and the first semiconductor layer 90a overlaps the gate electrode 64. The source and drain electrodes 94 and 96 are spaced apart from each other over the first semiconductor layer 90a. 
A transparent pixel electrode 110 is formed in each pixel region P. The pixel electrode 110 contacts the drain electrode 96.
A metal pattern 86 with an island shape is formed over a part of the gate line 62. The metal pattern 86 may be formed of the same material and in the same layer as the source and drain electrodes 94 and 96. The metal pattern 86 contacts the pixel electrode 110.
The gate line 62 and the metal pattern 86 constitute a storage capacitor Cst. The gate line 62 functions as a first electrode of the storage capacitor Cst, and the metal pattern 86 functions as a second electrode of the storage capacitor Cst.
A second semiconductor layer 90b is formed under the metal pattern 86, and a third semiconductor layer 90c is formed under the source and drain electrodes 94 and 96 and the data line 82 due to features of four-mask processes. Each semiconductor layer includes an intrinsic amorphous silicon layer and an impurity-doped amorphous silicon layer. The intrinsic amorphous silicon layer is exposed by the source and drain electrodes 94 and 96, the data line 82 and the data pad 84.
A manufacturing method of an array substrate for an LCD device using four mask processes according to the related art will be explained hereinafter with reference to attached drawings.
FIG. 3A through FIG. 9C illustrate a manufacturing method of an array substrate for an LCD device according to the related art.
FIGS. 3A, 3B and 3C illustrate a first mask process and correspond to cross-sections along the lines IIIA-IIIA, IIIB-IIIB and IIIC-IIIC of FIG. 2, respectively.
As shown in FIGS. 3A, 3B and 3C, a pixel region P, which includes a switching region S, a storage region C, a gate region G, and a data region D are defined on a substrate 60. The storage region C is defined as a part of the gate region G.
A gate line 62 and a gate electrode 64 are formed on the substrate 60 by sequentially depositing and then patterning a metallic material through a first mask process. The gate electrode 64 is connected to the gate line 62 and is disposed in the switching region S. The gate line 62 is disposed in the gate region G and includes a gate pad 66 at one end thereof. The gate line 62 and the gate electrode 64 may have a single-layered structure of aluminum (Al), an aluminum alloy such as AlNd, tungsten (W), chromium (Cr), or molybdenum (Mo) or may have a double-layered structure of Al/Cr or Al/Mo.
FIG. 4A through FIG. 7C illustrate a second mask process. FIGS. 4A, 5A, 6A and 7A correspond to cross-sections along the line IIIA-IIIA of FIG. 2. FIGS. 4B, 5B, 6B and 7B correspond to cross-sections along the line IIIB-IIIB of FIG. 2. FIGS. 4C, 5C, 6C and 7C correspond to cross-sections along the line IIIC-IIIC of FIG. 2.
As shown in FIGS. 4A, 4B and 4C, a gate insulating layer 68, an intrinsic amorphous silicon layer (a-Si:H) 70, an impurity doped amorphous silicon layer (n+ or p+ a-Si:H) 72, and a metal layer 74 are sequentially formed on a substantial part of the entire surface of the substrate 60. The substrate 60 includes the gate electrode 64 and the gate line 62, which includes a gate pad 66 at one end thereof.
The gate insulating layer 68 is formed by depositing a material selected from an inorganic insulating material group including silicon nitride (SiNX) and silicon oxide (SiO2) or an organic insulating material group including benzocyclobutene (BCB) and acrylic resin. The metal layer 74 is formed by depositing one or more materials selected from a metallic material group including aluminum (Al), an aluminum alloy such as AlNd, tungsten (W), chromium (Cr), molybdenum (Mo), a double-layered structure of Al/Cr and a double-layered structure of Al/Mo.
A photoresist layer 76 is formed on the metal layer 74 by coating. A mask M, which includes a transmitting portion B1, a blocking portion B2 and a half transmitting portion B3, is disposed over the photoresist layer 76. The blocking portion B2 corresponds to a part of the switching region S, the data region D, and the storage region C. The half transmitting portion B3 corresponds to the other part of the switching region S, i.e., a center part of the switching region S. The transmitting portion B1 corresponds to the other regions excluding the switching region S, the storage region C and the data region D.
Then, the photoresist layer 76 is exposed to light through the mask M and then is developed.
As shown in FIGS. 5A, 5B and 5C, a first photoresist pattern 78a, a second photoresist pattern 78b and a third photoresist pattern 78c are formed in the switching region S, the data region D and the storage region C, respectively. The first photoresist pattern 78a includes a first part of a first thickness and a second part of a second thickness. The second part corresponds to the center part of the switching region S, and the second thickness is thinner than the first thickness. The second photoresist pattern 78b extends from the first photoresist pattern 78a. The second photoresist pattern 78b and the third photoresist pattern 78c have the first thickness. The metal layer 74 is exposed in the other regions except for the switching region S, the data region D and the storage region C.
Then, the exposed metal layer 74, the impurity-doped amorphous silicon layer 72 and the intrinsic amorphous silicon layer 70 are partially removed. The metal layer 74 may be partially removed simultaneously with the partial removal of the impurity-doped amorphous silicon layer 72 and the intrinsic amorphous silicon layer 70 depending on a material of the metal layer 74. Alternatively, after the metal layer 74 is etched, the impurity-doped amorphous silicon layer 72 and the intrinsic amorphous silicon layer 70 may be dry-etched.
Accordingly, as shown in FIGS. 6A, 6B and 6C, a source-drain pattern 80 is formed under the first photoresist pattern 78a, a data line 82 including a data pad 84 at one end thereof is formed in the data region D, and a metal pattern 86 with an island shape is formed in the storage region C. The data line 82 is connected to the source-drain pattern 80.
A first semiconductor pattern 90a is formed under the source-drain pattern 80, a second semiconductor pattern 90b is formed under the data line 82 including the data pad 84, and a third semiconductor pattern 90c is formed under the metal pattern 86. Each of the first, second and third semiconductor patterns 90a, 90b and 90c includes the patterned intrinsic amorphous silicon layer 70 and the patterned impurity-doped amorphous silicon layer 72.
Then, the second part of the first photoresist pattern 78a is removed through an ashing process to thereby expose a part of the source-drain pattern 80. The first part of the first photoresist pattern 78a, the second photoresist pattern 78b and the third photoresist pattern 78c are partially removed. Thus the thicknesses of the first part of the first photoresist pattern 78a, the second photoresist pattern 78b and the third photoresist pattern 78c are reduced, and edges of the source-drain pattern 80, the data line 82, the data pad 84 and the metal pattern 86 are exposed.
As shown in FIGS. 7A, 7B and 7C, the exposed the source-drain pattern 80 and the impurity-doped amorphous silicon layer 72 thereunder are removed after the ashing process to thereby expose the intrinsic amorphous silicon layer 92a of the first semiconductor layer 90a. Therefore, source and drain electrodes 94 and 96 and an ohmic contact layer 92b are formed. The intrinsic amorphous silicon layer 92a of the first semiconductor layer 90a functions as an active layer.
The metal pattern 86 and the gate line 62 in the storage region C constitute a storage capacitor Cst with the gate insulating layer 68 therebetween. The gate line 62 functions as a first electrode of the storage capacitor Cst, and the metal pattern 86 functions as a second electrode of the storage capacitor Cst. The third semiconductor pattern 90c is interposed between the gate line 62 and the metal pattern 86.
Then, the first, second and third photoresist patterns 78a, 78b and 78c are removed. Thus, the second mask process is completed.
FIGS. 8A, 8B and 8C illustrate a third mask process and correspond to cross-sections along the line IIIA-IIIA, IIIB-IIIB and IIIC-IIIC of FIG. 2, respectively.
As shown in FIGS. 8A, 8B and 8C, a passivation layer 100 is formed on an entire surface of the substrate 60 including the source and drain electrodes 94 and 96, the data line 82 including the data pad 84, and the storage capacitor Cst thereon by depositing a material selected from an inorganic insulating material group including silicon nitride (SiNX) and silicon oxide (SiO2) or an organic insulating material group including benzocyclobutene (BCB) and acrylic resin.
The passivation layer 100 is patterned to thereby form a drain contact hole 102, a storage contact hole 104, a gate pad contact hole 106, and a data pad contact hole 108. The drain contact hole 102, the storage contact hole 104, the gate pad contact hole 106 and the data pad contact hole 108 expose the drain electrode 96, the metal pattern 86, the gate pad 66 and the data pad 84, respectively.
FIGS. 9A, 9B and 9C illustrate a fourth mask process and correspond to cross-sections along the line IIIA-IIIA, IIIB-IIIB and IIIC-IIIC of FIG. 2, respectively.
As shown in FIGS. 9A, 9B and 9C, a pixel electrode 110 is formed on an entire surface of the substrate 60 including passivation layer 100 thereon by sequentially depositing and then patterning a material selected from a transparent conductive group including indium tin oxide (ITO) and indium zinc oxide (IZO). Simultaneously, a gate pad terminal 112 and a data pad terminal 114 are formed. The pixel electrode 110 is disposed in the pixel region P, and the pixel electrode 110 contacts the drain electrode 96 through the drain contact hole 102 and the metal pattern 86 through the storage contact hole 104. The gate pad terminal 112 contacts the gate pad 66 through the gate pad contact hole 106. The data pad terminal 114 contacts the data pad 84 through the data pad contact hole 108.
An array substrate for the liquid crystal display device of the related art may be fabricated through the four mask processes as disclosed above. Fabricating processes and costs are may be reduced compared to five or six mask processes, and problems may decrease due to the shortened processes.
However, there exists a need to reduce fabricating time and costs by further simplifying the processes.